Conventional dynamic random access memory (DRAM) cells typically utilize a single capacitor (1C) to retain charge representing a “1” or “0” data value and one transistor (1T) having a current carrying terminal (e.g., source terminal) connected to an electrode of the capacitor and a gate terminal connected to a word line. This transistor is frequently referred to as a memory cell access transistor.
More recently, DRAM fabrication techniques have been proposed to reduce a complexity of fabricating conventional 1T/1C DRAM devices. These techniques include methods of forming capacitor-free DRAM cells. FIG. 1 is a cross-sectional view of a capacitor-free DRAM cell according to the prior art. As illustrated by FIG. 1, a relatively high voltage may be applied to a gate region 20 and a drain region 11 of a cell transistor to thereby cause impact ionization within a channel region 13 of the transistor. This ionization can result in the generation of a relatively high concentration of electron-hole pairs. This generation of electron-hole pairs may result in the accumulation of excess holes 1 within the channel region 13 of the cell transistor. These excess holes 1 may also be confined within the channel region 13 by using an oxide barrier layer 10 as an underlying layer that spans the source region 12, the channel region 13 and the drain region 11. This confinement of excess holes 1 may be treated as a form of charge storage that represents a logic 1 value in the DRAM cell.
Unfortunately, because a quantity of the excess holes 11 naturally decays in response to electron-hole recombination in the channel region 13, the cell transistor must be periodically refreshed to reestablish the necessary quantity of holes to reflect the stored logic 1 value. This requirement of periodic refreshing can limit the operation of a capacitor-free DRAM device, particularly if the rate at which refresh operations must be performed to reliably store data becomes excessive. One technique for reducing the refresh rate includes increasing the average retention time (i.e., lifetime) of excess holes in the channel region of a capacitor-free DRAM cell.